Please note this syllabus is updated continuously to reflect progress in the course, and update references to submitted lab reports.

Course Description

Objective

Gaining familiarity with common analog IC topologies through SPICE simulation analyses.

Note this class is not intended to be an in-depth analysis of specific circuits, this material will be covered in AIC-2.

The whole purpose of this class is to gain familiarity, experience and ultimately intuition for the operation of common analog IC topologies.

This is essential knowledge required to put our results and future circuit analyses in context (see AIC-2).

Textbook

The reference textbook we will use for this class is:

SPICE Simulation Software

The circuit simulator we will use for this class is:

The SPICE models device parameters we will use for this class are:

  • CMOS Devices (NCSU CDK):
    • 0.35uM Hewlett Packard GMOS10QA process
    • 0.35uM TSMC_CMOS035 process
  • Bipolar Devices (reference textbook): 20V bipolar process.

Assignments and Lab Reports

Assignments (to be done first)

Remember: every chapter must be read completely and each section must be understood and explained in your lab notebook (where circuits are covered) before the start of that section’s lab report, specifically:

  • Read textbook chapter
    • Define lab sections
  • For each individual section (only if circuit topologies are covered)
    • Understand each individual circuit topology
    • Write up (in lab notebook) circuit overview and explanation of results

Lab Reports (only necessary if circuit topologies are covered)

  • See the lab report template below for an example of what needs to be covered for every lab report.

  • Unless otherwise noted: individual lab reports need to be submitted for every topology section covered on each chapter.

  • Remember to update the “explanation of results” section to account for your own simulation results.

    • If there are significant differences, make sure to explain them in your report.

Submission Timelines

  • Individual section lab reports should be submitted every two to four weeks. (depending on the complexity of the circuit topology)

  • All the required section lab reports for each chapter should be completed in a month or less. i.e. so that we are covering at least a chapter per month.

Course Schedule

Lab Report Example Structure

Schematic Diagram

Here goes the Eeschema schematic diagram (SVG Format):

  • Width (default): 800 px width locked aspect ratio.

  • Page Margin: Fit to content.

SPICE Simulations

The SPICE analyses are normally different for every chapter, i.e. to be able to measure the performance characteristics of that specific topology, some examples:

Operating point Analysis

  • Description of SPICE analysis

  • Relevant source code lines

  • Labelled plots (SVG format)

Transient Analysis

DC Analysis

AC Analysis

Results

Describe the results of your simulation: figures of merit, error measurements …etc. Anything necessary to compare the performance of the circuit with other topologies.

Source Code

Preferably you should provide the individual links to the source code files used for the circuit simulation in this section.

Alternatively, you can provide the source code in this section verbatim.

References

Don’t repeat references on each report, simply provide a link to the previous report and syllabus.



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