The book does not provide simulation results for these pages, thus this report is simply a brief lab note for future reference.

Given a single current reference, how does one generate mutiple matched currents to be used for different circuit-blocks in an integrated circuit?

Bipolar Devices

As noted in the book (refer to pages 3-6 below), in the simplest case you can take the Widlar Current Mirror and connect additional transistors in parallel – base and emitters tied together. Then, for every output transistor you can connect their individual collectors to different circuit-blocks.

There is a problem however, the more output transistors you add in parallel, the larger the base current error of the mirror. To remedy this error, you can add an additional current buffer transistor Q3 (see the reference schematic in the book), this transistor provides the base current for all the current matching transistors from the power supply instead (with a very small base current taken from the reference). Now you can add a large number of output transistors with a very minor influence to the reference current.

On the other hand, this extra transistor introduces a small error: the collector voltages of Q1 and Q2 are no longer matched. We can partially compensate for this by adding emitter resistors (negative feedback) as explained in our Lab 3.4: Emitter Resistors (Negative Feedback). Keep in mind however, all of the emitter resistors for the output transistors must add up to match that of Q1’s single emitter resistor.

MOS Devices

As noted in the book (refer to pages 3-6 and 3-7 below), MOS devices do not have a DC gate current which fortunately means we can add as many output transistor devices as we want.

The only error to be concerned about is the current output dependence with drain voltage. To compensate for this error, we can utilize some of the techniques explored in previous lab reports e.g. adding source resistors (negative feedback) or using a Wilson Current Mirror topology (though this topology is not particularly optimal for MOS devices) among others.

A better alternative for MOS devices however, is to add a different cascode stage at the output of each mirror and we will explore this topology in the next lab report.

References



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