VLSI Design Methodology -- Class Resources
These learning resources are to be kept for reference to describe class projects completed during my graduate classes in Analog and RF IC design while at the University.
Please note there may be still typos, omissions or unfortunately some old learning mistakes in some of these (I am in the process of fixing them). If you could kindly let me know (issues or e-mail) I could fix them when I have a bit of time.
Project 1: Device and Circuit Characterization
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Device Characterization
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Inverter and Inverter Chain Characterization
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Inverter Layout Using Cadence Design Flow
Project 2: Circuit and Layout Design for Optimum Performance
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Circuit Characterization and Performance Estimation
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Schematic Entry and Transistor Level Simulation
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Layout Design and Post-layout Verification
Project 3: Design of an Unsigned 4x4 Array Multiplier
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Verilog/VHDL design of an unsigned 4x4 array multiplier
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Synthesis Using Standard Cells
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Place and Route
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