Designed the processors’ hardware architectures and developed the individual processors’ sub modules via the use of Verilog HDL to support a MIPS instructions set. Both processors were implemented using a FPGA.

EE 471 Final Report




Find a problem? Mistakes? File an Issue. You can reply on an existent thread related to this post, or otherwise create a new issue using the title of this post.

Comments? Drop me a note at the address below.